Designing high-speed electronic products brings many challenges. High-speed busses such as PCI-Express, DDRx, and serial ATA run at frequencies from several hundred megahertz to more than a gigahertz, making for tight timing margins.
Fine-geometry silicon generates fast edge rates. And growing pressure for smaller and cheaper products leads to very dense printed circuit board (PCB) layouts. To implement a successful high-speed PCB design, all these factors must be taken into consideration.
There are three main areas of concern when creating electronic products with high-speed design constraints: signal quality, timing, and crosstalk.
By analysing these areas you can improve product reliability and quality by testing what-if scenarios, generating routing constraints, and validating them in layout to ensure your electrical requirements are met. Through analysis, you can also drive sensible decisions about trace lengths, topology, spacing, and part placement, and constrain items such as board stackup, trace widths, and copper weights.
Digital logic reduces data to a series of 1s and 0s, which are represented in a real system by high and low voltages. In order for a receiver to determine whether or not a voltage represents a 1 or a 0, that voltage must be above or below the logic thresholds of the receiver. Also, that voltage must not exceed the limits of the receiver or it might be damaged. These two requirements generate two fundamental constraints in signal quality analysis: ringback and overshoot.
If a designer or engineer were to just connect a transmitter to a receiver, the result would be something like the waveform shown in Fig. 1 a on the left. Here, we can see there are both ringback and overshoot violations. The waveform shows negative overshoot in excess of 1V. It also rings back to 0,8 V, which is the lower logic threshold. If a PCB were built with this topology as is, errors in the data stream would occur and the receivers could be damaged. If the length of the topology is reduced significantly, to well below the length of our signal edges, the receiver waveform is cleaned up dramatically. This can be seen in Fig. 1 b on the right side. Unfortunately, however, such lengths are typically in the order of 2,5 cm or so, which is not always feasible in a design.
Another method of cleaning up the signal at the receiver is to use termination to match the impedance of the drivers and receivers to the board traces. This lets you control the reflections that create overshoot and ringback violations. Termination also allows for greater flexibility in topology length as trace lengths aren’t restricted to an unrealistic maximum and cleaner signals can be obtained. Termination values may be taken from bus design guidelines or, in the absence of such guidelines, determined from analysis. Powerful HyperLynx technology, integrated within the PADS flow, takes this a step further with the Termination Wizard, which can determine ideal termination values automatically by looking at the topology.
The location of the terminator within the trace topology can also be determined by varying those lengths and analysing the results. Maximum length rules for determining where the terminators should be placed are created from this analysis, as are length constraints for the other traces in the topology. An example of this is shown in Fig. 2. All these lengths may be explored in order to create the widest solution space that still meets the signal quality requirements.
Most length constraints in a design are driven from a timing need. Timing needs come from the fact that data is “clocked in” to a receiver at certain intervals. If the data are not there when the system needs them to be, the system doesn’t work. There are two main types of bus timing architectures: common clock and source synchronous. These lead to two types of layout constraints: min/max and matched lengths. Minimum and maximum delay constraints are created from common clock bus architectures.
An example of this is PCI, where data are clocked out of a transmitter and into a receiver using a common clock. In order to make sure the data are not there too early, or violate the hold-time requirement, a minimum length constraint must be created. Similarly, to ensure that data do not arrive too late, a maximum length constraint is created. These constraints are not based merely upon the length of the line.
Many other considerations, such as receiver loading and signal quality issues, determine when the transmitted data may be valid at the receiver, so proper signal analysis is critical for calculating these lengths appropriately. Matched delay constraints come about from source-synchronous busses. These busses, such as DDRx, send a clocking signal or “strobe” along with the data in order to “clock it in” at the receiver. This eliminates the complex timing relationship between driver and receiver, and requires only the matching of the strobe to the data. Typically, these interfaces have other concerns, such as signal quality, which determine when the data are valid. The main timing constraint for these busses is the matched delay constraint, which becomes tighter with increases in bus speed or signal quality problems.
Another important constraint for the layout of the design is the spacing between traces. This is determined by the amount of crosstalk that occurs between the signals. A number of factors influence crosstalk, including the edge rate of the driver, the board stackup, the amount of parallelism between traces, and the spacing between traces.
Crosstalk affects both signal quality and timing, and the amount of crosstalk allowed on a given net can be determined from simulation. An example of a crosstalk simulation is shown in Fig. 3.
Crosstalk analysis typically consists of a “victim” trace and two “aggressor” traces. More aggressors can be included but, in most cases, 95% of the crosstalk comes from the nearest two. With models for the driver, the receiver, and the board stackup built into the simulation, you can modify the spacing between the traces to determine an acceptable level of crosstalk. You can also modify the length that the traces run parallel and view the effects. The main result of such an analysis is a spacing rule between traces. If that spacing rule cannot be met, or if greater flexibility is to be allowed in the layout, a rule could be created with tighter spacing and a maximum parallelism constraint. Such a pair of constraints can be created from crosstalk analysis and modified as demands change.
Once all the necessary routing constraints have been created and you’ve routed the board using those constraints, it is good practice to verify that the board meets the original electrical requirements that prompted those constraints. A good way to close the loop is to do a post-route analysis of all the nets on the board. Fig. 4 highlights an example from the batch mode wizard in PADS.
In Fig. 4, note that PADS uses HyperLynx to run a simulation directly on the layout data and to verif y the design against overshoot, delay, and crosstalk constraints. If nets are found that violate any of these constraints, these nets can be simulated one at a time to be looked at in more detail. Post-route analysis is an excellent complement to the rigorous pre-route or “what-if ” analysis that is performed earlier in the design cycle. It is another step in the series of tasks performed to analyse high-speed busses. Without these types of analyses, and the constraints created as results, modern digital systems could not be designed to meet the cost, size, and performance needs of today.
How PADS can help
The PADS product creation platform gives individual designers and electrical engineers a competitive advantage, providing the tools needed to resolve electronic product-design challenges. From concept to fabrication, PADS helps ensure quality and reliability throughout the design cycle. Choose the perfect configuration for your needs and budget. Scalable, intuitive solutions provide the horsepower needed to design, validate, and manufacture PCB-centric electronic products in easy-to-use suites that enable even casual or occasional users to accelerate time to productivity. Solutions are also available for customers working in global enterprise companies and for those with multi-gigabit, SERDES, electromagnetic, and electrical rule design challenges.
Contact Charl Peters, ASIC Design Services, Tel 011 315-8316, email@example.com