Avionic and radar systems soar with multicore DSPs

September 14th, 2012, Published in Articles: EngineerIT

by Hector Rivera and Tom Flanagan, Texas Instruments, USA

Today’s complex radar and avionics systems require high processing capabilities – but face restrictive size, weight and power (SWaP) constraints. The functions driving these systems are signal processing-intensive. They benefit greatly from efficient implementations of digital signal processing (DSP) algorithms executed on size, performance and power efficient processors.

Fig. 1: TMS320C6657/55 block diagram.

These systems also have evolving requirements in design and data usage. In order to meet the requirements of SWaP efficiency and adaptability, programmable DSPs and systems-on-chip (SoCs) have become the processing platform of choice. They provide unmatched signal processing at very low power levels for radar and avionics, as well as software-defined radios (SDR), imaging and video applications that often accompany radar and avionics.

Keeping up with the growing demand for SWaP efficient SoCs is challenging. They must cost effectively deliver performance while meeting objectives of low power consumption to address operational and environmental targets. KeyStone devices are offered in a range of capacities with software compatibility throughout the range. This makes addressing diverse requirements or designing with future growth in mind straightforward and developmentally efficient.

Fixed and floating point processing

The use of multiple digital signal processor (DSP) cores is a key technology enabling increasingly sophisticated signal processing to advance the state of the art in waveformintensive applications, such as avionics, radar, sonar, signal intelligence (SIGINT), image and video processing and SDR. Multicore capabilities, combined with an expanding array of AccelerationPacs and development tools for multicore DSPs, enable high performance at exceptionally low performance/watt in compact form factors.

Avionics, radar and related applications need multicore DSPs to meet the advancing requirements of these mission critical applications including higher processing throughput, finer resolution, increased accuracy and the integration of advanced I/O. Many of these functions rely on floating point math to achieve the required precision. The KeyStone architecture provides significant flexibility to the designer by providing floating or fixed point execution within a single device on an instruction by instruction basis. And, the floating point operations execute at clock rates up to 1,25 GHz – rates normally only reserved for fixed point devices. Designers no longer have to sacrifice performance to gain floating point accuracy or complicate designs with separate fixed and floating point processors.


In addition to exceptional DSP performance, the C6657/55 features Viterbi and Turbo AccelerationPacs for processing communications and waveform algorithms in low power hardware while taking advantage of the 1MB L2 memory per core and 1MB of shared memory. These AccelerationPacs operate independently from the programmable cores, freeing up DSP resources for other processing, thereby reducing latencies and streamlining software development. The KeyStone architecture’s Multicore Navigator provides a hardware-based abstraction layer that liberates software developers from the specifics of the underlying hardware, as its queues and descriptors are used to automatically direct software tasks to the appropriate resource, providing scalability and resource pooling as an integral function of the processor. It can run on any KeyStone device, providing scalability from one to many DSP cores without changes. Together, these elements provide high performance at low power levels demanded by SWaP-oriented applications. Fig. 1 depicts a functional diagram of the C6657.

High performance I/O

Quite often, these systems need to interoperate with equipment from multiple vendors and other legacy systems. The DSP has a high-performance peripheral set supporting both the high data transfer rates required by modern systems as well as the flexibility to support legacy designs. It takes advantage of the rich peripherals and AccelerationPacs in the KeyStone architecture to provide full multicore entitlement in a compact and power efficient form factor.

The SRIO, PCIe, and HyperLink provide high-speed interconnects between multiple SoCs and/or FPGAs. HyperLink, an interface extension of the KeyStone architecture’s internal bus, provides 50 Gbps in a point-to-point high speed interconnect. HyperLink provides a low overhead protocol and high-speed communication and connectivity to other KeyStone devices or FPGAs. It provides a solution to the scalability requirement in today’s radar, SDR, and avionics systems. Alternately, SRIO and PCIe provide standards-based interconnect at lower bit rates.

The 32 bit DDR3 external memory interface (with ECC) provides 1,333 MHz busses with 8 GB of addressable memory space. DDR3 implementation reduces latency associated with external memory access and provides the speed necessary to support the large amounts of data associated with these applications.

Size and power

SWaP is a major requirement for the mission critical applications addressed above. The C6657 provides dual C66x DSP power, yet dissipates only 3,5 W or less at 1 GHz while delivering an ideal combination of performance and peripherals to address market needs. The devices are also provided in a new low profile “thin” package (2,9 mm in height), optimising the overall system level packaging required for mission critical. In addition, these devices are available in extended temperature ranges of -55 to 100°C, which are often called for in avionics applications.

Additionally, the device can support the most complex waveform in software defined radios. The VCP and TCP3d accelerators, the internal share memory (up to 3 MB) and the interface bandwidth provide the necessary performance to support and generate the most complex waveform used in many SDR applications.

Radar design requirements

Modern radar designs are incorporating signal-processing functions at the front end (exciter/receiver) of the radar system. This may include waveform generation, filtering, matrix-inverse operations, and signal correlation. There are also math functions in radar systems, which include recursive least-square and square-root operations. Many designers have implemented these functions in C-based processors (in fixed-decimal and/or floating-point operations). These types of designs can take advantage of the small form factor and dual fixed/floating cores provided in the DSP to meet systems requirements.

For example, in adaptive-array designs and standard spatial transceiver-array processing (STAP), matrix inversion is an important element. Depending on the size of the array used in the radar system the matrix inversion can take advantage of parallel processing provided by the DSP to reduce latency and improve the power dissipation of the system. As the size of the array in the system increases, the floating-point multiplication required increases. The most likely design path for radar system designers is to implement this function using DSP and internal memory blocks. It provides up to 40 GFLOPs and 3 MB of internal memory of performance and is an excellent fit for this application.


The combination of peripherals and processing power provided by these DSPs brings many benefits to system design, including floating point performance at fixed point speeds, improved system flexibility, and reduced system cost and power. The peripherals included on the devices provide network connectivity (EMAC), a high-speed memory interface with ECC, standard bus interfaces (PCIe) and a high speed, low latency point-to-point interface (HyperLink). This advanced peripheral set enhances system performance and scalability and, due to integration, further reduces system cost. The combined fixed and floating point numerical performance of the DSP provides a natural advantage when it comes to running the complex computationally intensive algorithms required for radar, SDR and avionics applications.

Contact Rodney Farrow, Texas Instruments, Tel 011 969-3245,